Toshiba & Western Digital are preparing a 128-layer 3D NAND memory

By Prosyscom
In March 11, 2019
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The companies Western Digital and Toshiba have jointly developed 128-layer chip flash memory 3D NAND TLC with a capacity of 512 GB (64 GB), which is 33% higher than the previous 96-layer memory. Item Toshiba, this chip will be called BiCS-5 (BiCS-4 – 96-layer and BiCS-3 – 64-layer flash memory).

It is reported that the crystal BiCS-5 has a layout with four separate sections or planes (planes), each of which you can get independent access. For comparison, IC BiCS 3 BiCS and a-4 used a two-plane structure. In absolute values it is allowed to double the write speed per channel is more than doubled: from 57 MB/s up to 132 MB/s.

In addition, the new chips used design Circuit-under-Array (CuA), which implies that the logic control circuits in the lower plane. Due to this, the dimensions of the crystal are reduced by 15% compared to chips without CuA.

Also, the engineers of the companies had decided to carry out data access pages in the 4 KB to reduce power consumption. In existing storage pages are used for 16 KB.

Senior analyst at Wells Fargo, Aaron Rakers (Aaron Rakers) claims that Toshiba and Western Digital offers the industry a high chip density with 85% yield of the plates. Commercial use of the 128-layer 3D NAND chips could begin as early as next year.

Toshiba и Western Digital готовят 128-слойную память 3D NAND
Toshiba и Western Digital готовят 128-слойную память 3D NAND



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